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DATA SHEET
PCF8811 80 x 128 pixels matrix LCD driver
Product specification Supersedes data of 2002 Dec 04 2004 May 17
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 10 10.1 11 11.1 11.2 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS ROW 0 to ROW 79: row driver outputs COL 0 to COL 127: column driver outputs VSS1 and VSS2: negative power supply rails VDD1 to VDD3: positive power supply rails VOTPPROG: OTP programming power supply VLCDOUT, VLCDIN and VLCDSENSE: LCD power supply T1 to T5: test pads MF2 to MF0 DS0 VOS4 to VOS0 EXT: extended command set PS0, PS1 and PS2 D/C R/W E SCLH/SCE SDAH SDAHOUT DB7 to DB0 OSC: oscillator RES: reset BLOCK DIAGRAM FUNCTIONS Oscillator Address Counter (AC) Display Data RAM (DDRAM) Timing generator Display address counter LCD row and column drivers ADDRESSING Display data RAM structure PARALLEL INTERFACE 6800 series parallel interface SERIAL INTERFACING (SPI AND SERIAL INTERFACE) Serial peripheral interface Serial interface (3-line) 12 12.1 12.2 12.3 13 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 14 15 16 17 18 19 20 21 22 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 23 24 25 26 27 28 29 30 I2C-BUS INTERFACE
PCF8811
Characteristics of the I2C-bus (Hs-mode) I2C-bus Hs-mode protocol Command decoder INSTRUCTIONS Explanation of the symbols Initialization Reset function Power-save mode Display control Set Y address of RAM Set X address of RAM Set display start line Bias levels Set VOP value Temperature control LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS PARALLEL INTERFACE TIMING CHARACTERISTICS SERIAL INTERFACE TIMING CHARACTERISTICS I2C-BUS INTERFACE TIMING CHARACTERISTICS APPLICATION INFORMATION MODULE MAKER PROGRAMMING VLCD calibration Temperature coefficient selection Seal bit OTP architecture Interface commands Example of filling the shift register Programming flow Programming specification CHIP INFORMATION BONDING PAD LOCATIONS DEVICE PROTECTION DIAGRAM TRAY INFORMATION DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
1 FEATURES
PCF8811
* Single-chip LCD controller/driver * 80 row and 128 column outputs * Display data RAM 80 x 128 bits * 128 icons (row 80 can be used for icons in extended command set and when icon rows are enabled) * An 8-bit parallel interface, 3 or 4-line Serial Peripheral Interface (SPI) and high-speed I2C-bus * On-chip: - Configurable voltage multiplier generating VLCD; external VLCD also possible - Linear temperature compensation of VLCD; 8 programmable temperature coefficients (extended command set); one fixed temperature coefficient which default can be set by OTP programming (basic command set) - Generation of intermediate LCD bias voltage - Oscillator requires no external components; external clock input also possible. * OTP calibration for VLCD and accurate frame frequency * External reset input pin * CMOS compatible inputs * Mux rate: 1 : 16 to 1 : 80 in steps of 8 when no icon row is used, with the icon row steps of 16 can be used * Logic supply voltage range VDD1 - VSS: - 1.7 V to 3.3 V. * High voltage generator supply voltage range VDD2,VDD3 - VSS: - 1.8 V to 3.3 V. * Display supply voltage range VLCD - VSS: - 3 V to 9 V. * Low power consumption; suitable for battery operated systems 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8811U/2DA/1 PCF8811MU/2DA/1 - - DESCRIPTION chip with bumps in tray, not covered under Philips/Motif license agreement chip with bumps in tray, sold under license from Motif VERSION - - * Programmable bottom row pads mirroring; for compatibility with both Tape Carrier Packages (TCP) and Chip On Glass (COG) applications (extended command set) * Status read which allows for chip recognition and content checking of some registers * Start address line which allows, for instance, the scrolling of the displayed image * Programmable display RAM pointers for variable display sizes * Slim chip layout, suited for COG applications * Temperature range: Tamb = -40 C to +85 C. 2 APPLICATIONS
* Telecom equipment * Portable instruments * Point of sale terminals. 3 GENERAL DESCRIPTION
The PCF8811 is a low power CMOS LCD controller driver, designed to drive a graphic display of 80 rows and 128 columns or a graphic display of 79 rows and 128 columns and a icon row of 128 symbols. All necessary functions for the display are provided in a single chip, including on-chip generation of the LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8811 can interface to microcontrollers via a parallel bus, serial bus or I2C-bus interface.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
5 BLOCK DIAGRAM
PCF8811
VDD1
VDD2
VDD3
COL 0 to COL 127
ROW 0 to ROW 79
128
80
COLUMN DRIVERS BIAS VOLTAGE GENERATOR DATA PROCESSING
ROW DRIVERS
VLCDIN
VSS1 VSS2 VOTPPROG VLCDSENSE VLCDOUT T1 T2 T3 T4 T5 MF [2:0] DS0
3
ORTHOGONAL FUNCTION GENERATOR
RESET HIGH VOLTAGE GENERATOR DISPLAY DATA RAM 80 x 128 bits OSCILLATOR
RES
OSC
TIMING GENERATOR ADDRESS COUNTER DISPLAY ADDRESS COUNTER
COMMAND DECODER
PCF8811
I/O BUFFER PARALLEL/SERIAL/I 2C-BUS INTERFACE
5 3
mgw732
DB7/SDATA
DB6/SCLK
DB4
DB3/SA1
DB2/SA0
DB1
Fig.1 Block diagram.
2004 May 17
SCLH/SCE
4
SDAHOUT
DB5/SDO
VOS [4:0]
PS [2:0]
SDAH
EXT
R/W
DB0
D/C
E
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
6 PINNING SYMBOL MF2 MF1 MF0 DS0 OSC EXT PS0 PS1 PS2 VSS(tie off) SDAHOUT SDAH SCLH/SCE VOTPPROG RES D/C R/W E VDD(tie off) DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SDO DB6/SCLK DB7/SDATA VDD1 VDD2 VDD3 VSS1 VSS2 T5 T2 T1 T4 T3 VOS4 VOS3 VOS2 2004 May 17 PAD 9 10 11 12 13 14 15 16 17 18 19 20 and 21 22 and 23 24 to 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 to 45 46 to 55 56 to 60 61 to 70 71 to 80 81 82 83 84 85 86 87 88 parallel data input/output parallel data input/output parallel data input/output or I2C-bus slave address input parallel data input/output or I2C-bus slave address input parallel data input/output parallel data input/output or serial data output parallel data input/output or serial clock input parallel data input/output or serial data input general supply voltage supply voltage for the internal voltage generator supply voltage for the internal voltage generator ground ground test input 5 test input 2 test input 1 test output 4 test output 3 VLCD offset input pad 4 VLCD offset input pad 3 VLCD offset input pad 2 5 I2C-bus data output I2C-bus data input I2C-bus clock input/chip enable (6800 interface) manufacturer device ID input manufacturer device ID input manufacturer device ID input device recognition input oscillator input extended command set input parallel/serial/I2C-bus data selection input parallel/serial/I2C-bus data selection input parallel/serial/I2C-bus data selection input DESCRIPTION
PCF8811
supply voltage for OTP programming (can be combined with SCLH/SCE) external reset input data/command input read/write (6800 interface) input clock enable (6800 interface) input
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
SYMBOL VOS1 VOS0 VLCDOUT VLCDSENSE VLCDIN ROW 79 to ROW 40 ROW 80 COL 0 to COL 127 ROW 0 to ROW 39
PAD 89 90 91 to 99 100 101 to 107 115 to 154 155 156 to 283 284 to 323 1, 3 to 8, 109 to 114, 324 to 333 2 and 108 VLCD offset pad 1 VLCD offset pad 0 voltage multiplier output voltage multiplier regulation input LCD supply voltage
DESCRIPTION
LCD row driver outputs; ROW 79 is the icon row when the icon row is enabled duplicate of ROW 79 LCD column driver outputs LCD row driver outputs dummy pads
alignment marks 7.6 VLCDOUT, VLCDIN and VLCDSENSE: LCD power supply
7 7.1
PIN FUNCTIONS ROW 0 to ROW 79: row driver outputs
These pads output the display row signals. 7.2 COL 0 to COL 127: column driver outputs
These pads output the display column signals. 7.3 VSS1 and VSS2: negative power supply rails
The 2 supply rails must be connected together. 7.4 VDD1 to VDD3: positive power supply rails
VDD2 and VDD3 are the supply voltage for the internal voltage generator. Both have the same voltage and may be connected together outside of the chip. VDD1 is used as supply for the rest of the chip. VDD1 can be connected together with VDD2, VDD3 but in this case care must be taken to respect the supply voltage range; see Chapter 16. If the internal voltage generator is not used then pins VDD2 and VDD3 must be connected to VDD1. 7.5 VOTPPROG: OTP programming power supply
Positive power supply for the liquid crystal display. If the internal VLCD generator is used, then all three inputs must be connected together. If not (VLCD generator is disabled and an external voltage is supplied to VLCDIN), then VLCDOUT must be left open-circuit, VLCDSENSE must be connected to VLCDIN, VDD2 and VDD3 should be applied according to the specified voltage range. An external LCD supply voltage can be supplied using the VLCDIN pad. In this case, VLCDOUT should not be connected to VLCDIN, and the internal voltage generator must be switched off. If the PCF8811 is in power-save mode, the external LCD supply voltage can be switched off. 7.7 T1 to T5: test pads
T1, T2 and T5 must be connected to VSS, T3 and T4 must be left open-circuit. Not accessible to user. 7.8 MF2 to MF0
Manufacturer device ID pads. (manufacturer ID 100 = Philips). 7.9 DS0
Supply voltage for the OTP programming; see Chapter 22. VOTPROG can be combined with the SCLH/SCE pin in order to reduce the external connections.
Device recognition pad; see Table 10.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
7.10 VOS4 to VOS0 7.16 SCLH/SCE
PCF8811
These 5 input pins enable the calibration of the programmed VLCD (can be connected on the module to VDD1 or VSS1). 7.11 EXT: extended command set
Input to select the chip and so allowing data/commands to be clocked in or serial clock input when the I2C-bus interface is selected. 7.17 SDAH
Input to select the basic command set or the extended command set. Must be connected on the module to have only one command set enabled. Table 1 PIN EXT Command set LEVEL LOW HIGH DESCRIPTION basis command set extended command set
I2C-bus
serial data input. When not used it must be connected to VDD1 and VSS1. SDAHOUT
7.18
Note: Philips strongly recommends that the extended command set be used. 7.12 PS0, PS1 and PS2
Parallel/serial/I2C-bus interface selection. Table 2 Interface selection PS[2:0] 000 001 010 011 100 or 110 101 or 111 7.13 D/C INTERFACE 3-line SPI 4-line SPI no operation 6800 parallel interface high-speed I2C-bus interface 3-line serial interface
SDAHOUT is the serial data acknowledge output for the I2C-bus interface. By connecting SDAHOUT to SDAH externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in COG applications. In COG applications where the track resistance from the SDAHOUT pad to the system SDAH line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It is possible that during the acknowledge cycle the PCF8811 will not be able to create a valid logic 0 level. By splitting the SDAH input from the SDAHOUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid low level. When not used it must be connected to VDD1 or VSS1. 7.19 DB7 to DB0
These input/output lines are used by the several interfaces as described below. When not used in the serial interface or the I2C-bus interface it must be connected to VDD1 or VSS1. 7.19.1 DB7 TO DB0 (PARALLEL INTERFACE)
Input to select either command/data or data input. Not used in the 3-line serial interface, 3-line SPI and I2C-bus interface and must be connected to VDD1 or VSS1. 7.14 R/W
8-bit bidirectional bus. DB7 is the MSB. 7.19.2 DB7, DB6 AND DB5 (SERIAL INTERFACE)
Input to select read or write mode when the 6800 parallel interface is selected. Not used in the serial and I2C-bus mode and must be connected to VDD1 or VSS1. 7.15 E
DB7 is used for serial input data (SDATA) when the serial interface is selected. DB6 (SCLK) is used for the serial input clock when the serial interface is selected. DB5 is used as the serial output of the serial interface (SDO). 7.19.3 DB3 AND DB2 (I2C-BUS INTERFACE)
E is the clock enable input for the 6800 parallel bus. Not used in the serial or I2C-bus interface and must be connected to VDD1 or VSS1.
DB3 and DB2 are respectively the SA1 and SA0 inputs when the I2C-bus interface is selected and can be used so that up to four PCF8811s can be distinguished on one I2C-bus interface. 7
2004 May 17
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
7.20 OSC: oscillator 8.4 Timing generator
PCF8811
When the on-chip oscillator is used this input must be connected to VDD1. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS1, the display is not clocked and may be left in a DC state. To avoid this the chip should always be put into Power-down mode before stopping the clock. 7.21 RES: reset
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus. 8.5 Display address counter
This signal will reset the device and must be applied to properly initialize the chip. The signal is active LOW. 8 8.1 BLOCK DIAGRAM FUNCTIONS Oscillator
The display is generated by simultaneously reading out the RAM content for 2, 4 or 8 rows depending on the selected current display size. This content will be processed with the corresponding set of 2, 4 or 8 orthogonal functions and so generating the signals for switching the pixels in the display on or off according to the RAM content. The possibility exists to set the p value for the display sizes 64 and 80 manually to p = 4. The display status (all dots on/off and normal/inverse video) is set by the bits DON, DAL and E in the command display control; see Table 6. 8.6 LCD row and column drivers
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD1. An external clock signal, if used, is connected to this input. 8.2 Address Counter (AC)
The address counter assigns addresses to the display data RAM for writing. The X address X[6:0] and the Y address Y[3:0] are set separately. 8.3 Display Data RAM (DDRAM)
The PCF8811 contains 80 row and 128 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed.
The PCF8811 contains an 80 x 128-bit static RAM which stores the display data. The RAM is divided into 10 banks of 128 bytes (10 x 8 x 128 bits). The icon row when enabled is always ROW 79 and therefore located in bank 9. During RAM access, data is transferred to the RAM via the parallel, serial interface or I2C-bus interface. There is a direct correspondence between the X address and the column output number.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
DPRAM
bank 0
top of LCD
R0
bank 1 R8
bank 2
R16
LCD
bank 3
R24
bank 9
R72
R79
MGW734
Fig.2 DDRAM to display mapping.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
9 ADDRESSING 9.1.1 BASIC COMMAND SET
PCF8811
Data is downloaded in bytes into the RAM matrix of the PCF8811 as indicated in Fig.2. The display RAM has a matrix of 80 by 128 bits. The columns are addressed by the address pointer. The address ranges are: X = 0 to 127 (1111111), Y = 0 to 9 (1001). The Y address represents the bank number. The X and Y address which are effectively used can be programmed thus in order to use the PCF8811 with different display sizes without additional loading of the microprocessor. Addresses outside these ranges are not allowed. The icon row when enabled is always ROW 79 and therefore located in bank 9. 9.1 Display data RAM structure
After a write operation the column address counter (X address) auto-increments by one, and wraps to zero after the last column is written. The number of columns (X address) after which the wrap around must occur can be programmed. The Y address counter does not auto-increment in the basic command set, the counter stops when a complete bank has been written to. In this case the Y address counter must be set (Y address see Table 5) to write the next bank (see Fig.3). When only a part of the RAM is used both X (X max) and Y (Y max) addresses can be set. The data order in the basic command set is as defined in Fig.3.
The mode for storing data into the data RAM is dependent on the selected command set.
handbook, full pagewidth LSB
0
MSB
LSB
Y max
MSB
0
X address Y address
X max
MGW735
Fig.3 Sequence of writing data bytes into the RAM (basic command set).
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
9.1.2 EXTENDED COMMAND SET
PCF8811
In the vertical addressing mode (V = 1) the Y address increments after each byte. After the last Y address (Y = 9), Y wraps around to 0 and X increments to address the next column (see Fig.5). The last Y address after which Y wraps to 0 can be programmed. In Fig.5 it can be seen that the X address is programmed to be 127, and the Y address is programmed to be 9. With X max and Y max the X and Y addresses can be programmed while the whole RAM is not being used. After the very last address the address pointers wrap around to address X = 0 and Y = 0 in both horizontal and vertical addressing modes.
9.1.2.1
Horizontal/vertical addressing
Two different addressing modes are possible with the extended command set: horizontal addressing mode and vertical addressing mode. In the horizontal addressing mode (V = 0) the X address increments after each byte. After the last X address, X wraps around to 0 and Y increments to address the next row (see Fig.4). The number of columns (last X address) after which the wrap around must occur can be programmed. In Fig.4 it can be seen that the X address is programmed to be 127, and the Y address is programmed to be 9. With X max and Y max the X and Y addresses can be programmed while the whole RAM is not being used.
handbook, full pagewidth
0 128 256 384 512 640 768 896
1 129 257 385 513 641 769 897
2 130 258 386 514 642 770 898
0
Y address
1024 1025 1026 1152 1153 1154 0 X address 1279 127 9
MGW736
Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0) (extended command set).
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
0 1 2 3 4 5 6 7 8 9 0
10 11
0
Y address
1279 X address 127
9
MGW737
Fig.5 Sequence of writing data bytes into the RAM with vertical addressing (V = 1) (extended command set).
9.1.2.2
Data order
The data order bit (DOR) defines the bit order (LSB or MSB on top) for writing into the RAM (see Figs 6 and 7). This feature is only available in the extended command set.
LSB handbook, full pagewidth
MSB
LSB
MGW738
MSB
Fig.6 RAM byte organisation, if DOR = 0 (extended command set).
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
MSB handbook, full pagewidth
LSB
MSB
MGW739
LSB
Fig.7 RAM byte organisation, if DOR = 1 (extended command set).
9.1.3
FEATURES AVAILABLE IN BOTH COMMAND SETS
9.1.3.1
Mirror X (MX)
The MX bit allows horizontal mirroring: when MX = 1 the X address space is mirrored; the address X = 0 is then located at the right side (X max) of the display (see Fig.8). When MX = 0 the mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.9).
handbook, full pagewidth
0
Y max
X max
X address Y address
0
MGW740
Fig.8 RAM format addressing (MX = 1) (both command sets).
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
0
Y max
0
X address Y address
X max
MGW741
Fig.9 RAM format addressing (MX = 0) (both command sets).
9.1.3.2
Mirror Y (MY)
The MY bit allows vertical mirroring: when MY = 1 the Y address space is mirrored; the address Y = 0 is then located at the bottom of the display (see Fig.10). When MY = 0 the mirroring is disabled and the address Y = 0 is located at top of the display (see Fig.11). The icon row, when enabled, will always be located in bank 9 and ROW 79.
handbook, full pagewidth
Y max
0
0
X address Y address
X max
MGW742
Fig.10 RAM format addressing (MY = 1) (both command sets).
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
0
Y max
0
X address Y address
X max
MGW743
Fig.11 RAM format addressing (MY = 0) (both command sets).
10 PARALLEL INTERFACE The parallel interfaces which can be selected is the 6800 series 8-bit bidirectional interface for communication between the microcontroller and the LCD driver chip. The selection of these interfaces is achieved with pins PS[2:0]; see Section 7.12. 10.1 6800 series parallel interface
Table 3 D/C 0 0 1 1
6800 series parallel interface function R/WR 0 1 0 1 OPERATION command data write read status register display data write none
The interface functions of the 6800 series parallel interface are given in Table 3.
The parallel interface timing diagram for the 6800 series is given in Chapter 18 (see Figs 35 and 36). The timing diagrams differ because the clock is connected (in Fig.35) to the enable (E) input. In Fig.36 the clock is connected to the chip select input (SCE) and the enable input (E) is tied HIGH.
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15
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
11 SERIAL INTERFACING (SPI AND SERIAL INTERFACE) Communication with the microcontroller can also occur via a clock-synchronized Serial Peripheral Interface (SPI). It is possible to select two different 3-line (SPI and serial interface) or a 4-line serial interface. Selection is achieved via PS[2:0]; see Section 7.12. 11.1 Serial peripheral interface 11.1.1 WRITE MODE
PCF8811
The serial peripheral interface is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver chip. The 3 lines are: SCE (chip enable), SCLK (serial clock) and SDATA (serial data). For the 4-line serial interface a separate D/C line is added. The PCF8811 is connected to the serial data I/O (SDA) of the microcontroller by two pins: SDATA (data input) and SDO (data output) connected together.
The display data/command indication may be controlled either via software or the D/C select pin. When the D/C pin is used, display data is transmitted when D/C is HIGH, and command data is transmitted when D/C is LOW (see Figs 12 and 13). When pin D/C is not used, the display data length instruction is used to indicate that a specific number of display data bytes (1 to 255) are to be transmitted (see Fig.14). The next byte after the display data string is handled as an instruction command. When the 3-line SPI interface is used the display data/command is controlled by software. If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. The next byte received will be handled as an instruction command (see Fig.15).
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGW744
Fig.12 Serial bus protocol: transmission of one byte.
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGW745
Fig.13 Serial bus protocol: transmission of several bytes.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
SCE
SCLK
SDATA
DB7 DB6 DB5 DB4
DB2 DB1 DB0 data
data
last data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 instruction
display length instruction and length data (two bytes)
display data string
MGW746
Fig.14 Transmission of several bytes.
handbook, full pagewidth
SCE
SCLK
SDATA
data
data
data
data
data
data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
MGW747
display data string
instruction
Fig.15 Transmission interrupted by SCE.
11.1.2
READ MODE (ONLY EXTENDED COMMAND SET)
The read mode of the interface means that the microcontroller reads data from the PCF8811. To do so the microcontroller first has to send a command (the read status command) and then the PCF8811 will respond by transmitting data on the SDO line. After that SCE is required to go HIGH (see Fig.16).
The PCF8811 samples the SDIN data on rising SCLK edges, but shifts SDO data on falling SCLK edges. Thus the microcontroller is supposed to read SDO data on rising SCLK edges. After the read status command has been sent, the SDIN line must be set to 3-state not later then the falling SCLK edge of the last bit (see Fig.16). The serial interface timing diagram is given in Chapter 19.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
SCE
RES
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2
DB1 DB0
SDO instruction
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 read out data
MGW748
Fig.16 Read mode SPI 3-line and 4-line.
11.2
Serial interface (3-line)
The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The 3 lines are: SCE (chip enable), SCLK (serial clock) and SDATA (serial data). The PCF8811 is connected to the SDA of the microcontroller by two pins: SDATA (data input) and SDO (data output) which are connected together. 11.2.1 WRITE MODE
Figures 18, 19 and 20 show the protocol of the write mode: * When SCE is HIGH, SCLK clocks are ignored; during the HIGH time of SCE the serial interface is initialized * SCLK must be LOW on the falling SCE edge (see Fig.37) * SDATA is sampled on the rising edge of SCLK * D/C indicates, whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is sampled on the first rising SCLK edge * If SCE stays LOW after the last bit of a command/data byte, the serial interface receives the D/C bit of the next byte on the next rising edge of SCLK (see Fig.19) * A reset pulse RES interrupts the transmission. The data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a command/data byte (see Fig.20).
The write mode of the interface means that the microcontroller writes commands and data to the PCF8811. Each data packet contains a control bit (D/C) and a transmission byte. If D/C is LOW, the following byte is interpreted as a command byte. The command set is given in Table 5. If D/C is HIGH, the following byte is stored in the display data RAM. After every data byte the address counter is incremented automatically. Figure 17 shows the general format of the write mode and the definition of the transmission byte. Any instruction can be sent in any order to the PCF8811; the MSB is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
Transmission Byte (TB) (command byte OR data byte) handbook, full pagewidth
D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB
D/C
TB
D/C
TB
D/C
TB
MGU278
Fig.17 Serial data stream; write mode.
handbook, full pagewidth
SCE
SCLK
SDIN
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGU279
Fig.18 Write mode: a control bit followed by a transmission byte.
handbook, full pagewidth
SCE
SCLK
SDIN
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C
MGU280
Fig.19 Write mode: transmission of several bytes.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
SCE
RES
SCLK
SDIN
D/C DB7 DB6 DB5 DB4
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D/C
DB7 DB6
MGU281
Fig.20 Write mode: interrupted by reset (RES).
11.2.2
READ MODE (ONLY EXTENDED COMMAND SET)
The read mode of the interface means that the microcontroller reads data from the PCF8811. To do so the microcontroller first has to send a command (the read status command) and then the following byte is transmitted in the opposite direction (using SDO) (see Fig.21). After that, SCE is required to go HIGH before a new command is sent. The PCF8811 samples the SDATA data on the rising SCLK edges, but shifts SDO data on the falling SCLK edges. Thus the microcontroller is supposed to read SDO data on rising SCLK edges.
After the read status command has been sent, the SDATA line must be set to 3-state not later then the falling SCLK edge of the last bit (see Fig.21). The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge (see Fig.40). The last rising SCLK edge sets SDO to 3-state after the delay time t4. The serial interface timing diagram is given in Chapter 19.
handbook, full pagewidth
SCE
SCLK
SDIN
D/C DB7 DB6 DB5 DB4
DB3 DB2 DB1 DB0
D/C
SDOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MGU282
Fig.21 Read mode serial interface 3-line.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
12 I2C-BUS INTERFACE 12.1 Characteristics of the I2C-bus (Hs-mode) 12.1.2 BIT TRANSFER
PCF8811
The I2C-bus Hs-mode is for bidirectional, two-line communication between different ICs or modules with speeds of up to 3.4 MHz. The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate, therefore the buffers on the SCLH and SDAH have open-drain outputs. This is the same for I2C-bus master devices which have an open-drain SDAH output and a combination of an open-drain, pull-down and current source pull-up circuits on the SCLH output. Only the current source of one master is enabled at any one time, and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 12.1.1 SYSTEM CONFIGURATION
One data bit is transferred during each clock pulse (see Fig.23). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 12.1.3 START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.24. 12.1.4 ACKNOWLEDGE
The system configuration is illustrated in Fig.22. Definitions of the I2C-bus terminology: * Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices.
Each byte of eight bits is followed by an acknowledge bit; see Fig.25. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.22 System configuration.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.23 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.24 Definition of START and STOP conditions.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.25 Acknowledge on the I2C-bus.
12.2
I2C-bus Hs-mode protocol
The PCF8811 is a slave receiver/transmitter. If data is to be read from the device, the SDAH pin must be connected, otherwise SDAH may be unused. Hs-mode can only commence after the following conditions: * START condition (S) * 8-bit master code (00001XXX) * Not-acknowledge bit (A). The master code has two functions: it allows arbitration and synchronization between competing masters at F/S-mode speeds, resulting in one winner. The master code also indicates the beginning of an Hs-mode transfer. These conditions are illustrated in Figs 26 and 27. As no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge (A). After this A bit, and the SCLH line has been pulled up to a HIGH level, the active master switches to Hs-mode and enables at tH the current-source pull-up circuit for the SCLH signal (see Fig.27). The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit, and receives an acknowledge bit (A) from the selected slave.
After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its current source pull-up circuit. The active master re-enables its current source again when all devices have been released and the SCLH signal reaches a HIGH level. The rising of the SCLH signal is done by a pull-up resistor and therefore is slower, the last part of the SCLH rise time is speeded up because the current source is enabled. Data transfer only switches back to F/S mode after a STOP condition (P). A write sequence after the Hs-mode is selected is illustrated in Fig.28. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, the remainder will ignore the I2C-bus transfer. After the acknowledgement cycle of a write (W), one or more command words will follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and D/C, plus a data byte (see Fig.28 and Table 4). The last control byte is tagged with a cleared MSB, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
Table 4 BIT Co Co and D/C definition LOGIC LEVEL 0 1 D/C 0 1 0 1 0 1 R/W N/A ACTION
PCF8811
last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RE-START condition another control byte will follow the data byte unless a STOP or RE-START condition is received data byte will be decoded and used to set-up the device data byte will return the status byte data byte will be stored in the display RAM RAM read back is not supported The data pointer is automatically updated and the data is directed to the intended PCF8811 device. If the D/C bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8811. At the end of the transmission the I2C-bus master issues a STOP condition (P) and switches back to the F/S-mode, however, to reduce the overhead of the master code, it is possible that a master can link a number of Hs-mode transfers, separated by repeated START conditions (Sr).
A read sequence is given in Fig.29 and again this sequence follows after the Hs-mode is selected. The PCF8811 will immediately start to output the requested data until a not-acknowledge is transmitted by the master. Before the read access, the user has to set the D/C bit to the appropriate value by a preceding write access. The write access should be terminated by a RE-START condition so that the Hs-mode is not disabled. After the last control byte, depending on the D/C bit setting, either a series of display data bytes or command data bytes may follow. If the D/C bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer.
handbook, full pagewidth
,,,,,,,,,, ,,,,,,,,,,
F/S-mode S MASTER CODE A Sr SLAVE ADD. R/W A
Hs-mode (current-source for SCLH enabled)
DATA (n bytes + ack.)
,, ,, ,,,, ,,,,
F/S-mode A/A P Hs-mode continues Sr SLAVE ADD.
MSC616
Fig.26 Data transfer format in Hs-mode.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
S SDAH
8-bit Master code 00001xxx
A
t1 tH
SCLH
1
2 to 5
6
7
8
9
Fs mode
Sr
7-bit SLA
R/W
A
n x (8-bit DATA
+
A/A)
Sr P
SDAH
SCLH
1
2 to 5
6
7
8
9
1 Hs-mode
2 to 5
6
7
8
9 If P then Fs mode If Sr (dotted lines) then Hs mode
tH = MCS current source pull-up = Rp resistor pull-up
tFS
MSC618
Fig.27 Data transfer timing format in Hs-mode.
handbook, full pagewidth
acknowledge from PCF8811
acknowledge from PCF8811
acknowledge from PCF8811
acknowledge from PCF8811
acknowledge from PCF8811
SS Sr 0 1 1 1 1 A A 0 A 1 D/C 10 slave address
control byte
A
data byte
A 0 D/C
control byte
A
data byte n 0 bytes MSB . . . . . . . . . . . LSB
AP
R/W Co
2n 0 bytes
Co
1 byte
MGW749
Fig.28 Master transmits in Hs-mode to slave receiver; write mode.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
acknowledgement from PCF8811 SS Sr 0 1 1 1 1 A A 1 A 10 slave address R/W
NOT acknowledgement from Master
status information
AP
STOP condition
MGW750
Fig.29 Master receives from slave transmitter (status register is read); read mode.
12.3
Command decoder
The command decoder identifies command words that are received on the I2C-bus: * Pairs of bytes: information in 2nd byte, first byte determines whether information is display or instruction data * Stream of information bytes after Co = 0: display or instruction data depending on last D/C. The most significant bit of a control byte is the continuation bit Co. If this bit is at logic 1, it indicates that only one data byte, either command or RAM data, will follow. If this bit is at logic 0, it indicates that a series of data bytes, either command or RAM data, may follow. The DB6 bit of a control byte is the RAM data/command bit D/C. When this bit is at logic 1, it indicates that a RAM data byte will be transferred next. If the bit is at logic 0, it indicates that a command byte will be transferred next. 13 INSTRUCTIONS The PCF8811 interfaces via an 8-bit parallel interface, two different 3-line serial interfaces, a 4-wire serial interface or an I2C-bus interface. Processing of the instructions does not require the display clock. Data accesses to the PCF8811 can be broken down into two areas; those that define the operating mode of the device, and those that fill the display RAM.
In the case of the parallel and 4-wire SPI interfaces, the distinction is the D/C pin. When the D/C pin is at logic 0, the chip will respond to instructions as defined in Table 5. When the D/C bit is at logic 1, the chip will send data to the RAM. When the 3-wire SPI, the 3-wire serial interface or the I2C-bus interface is used, the distinction between instructions which define the operating mode of the device and those that fill the display RAM, is made respectively by the display data length instruction (3-line SPI) or by the D/C bit in the data stream (3-line serial interface and I2C-bus interface). There are 4 types of instructions. Those which: 1. Define the PCF8811 functions, such as display configuration etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are used most frequently. A basic and an extended instruction set is available: if the EXT pin is set LOW the basic command set is used. If the EXT pin is set HIGH the extended command set is used. Both command sets are detailed in Table 5.
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 5 Instruction set; note 1 2004 May 17 2004 May 17 27 27 ADR commands Set initial display line Set initial row Philips Semiconductors
80 x 128 pixels matrix LCD driver 80 x 128 pixels matrix LCD driver
INSTRUCTION NOP NOP Reset Write data Display data length Status read Display control
EXT(2) X X X X X X X X X X X X X 1 1 1 1 X X X X
COMMAND BYTE D/C 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D7 1 D7 BUSY 1 1 1 1 1 1 1 1 1 1 1 0 0 0 X 0 X 0 X 0 X D7(3) 1 1 1 D6 1 D6 DON 1 0 0 0 0 1 1 0 1 1 0 0 0 0 X 0 X max6 1 L6 1 C6 DESCRIPTION D6 0 1 1 D5 1 D5 RES 0 1 1 1 1 0 1 1 1 1 1 0 0 0 X 0 X max5 0 L5 0 C5 D5 0 0 0 D4 0 D4 MF2 1 0 0 0 0 0 0 0 0 0 1 1 0 1 X 1 X max4 0 L4 0 C4 D4 1 0 0 D3 1 D3 MF1 1 1 0 0 0 MY 1 0 1 1 Y3 0 X3 1 Y max3 1 X max3 0 L3 0 C3 D3 1 1 0 D2 0 D2 MF0 0 1 1 1 0 X 1 0 0 1 Y2 X6 X2 0 Y max2 0 X max2 0 L2 1 C2 D2 X 0 1 D1 0 D1 DS1 1 1 1 0 0 X 1 1 1 0 Y1 X5 X1 0 Y max1 0 X max1 X L1 X C1 D1 X 0 0 D0 0 D0 DS0 X DON E DAL MX X IC V DOR BRS Y0 X4 X0 1 Y max0 0 X max0 X L0 X C0 set Y max; 0 Y 9 D0 no operation no operation soft reset write data to display RAM only used in 3-line SPI read status byte read status byte display on or off normal or reverse mode all pixels on or off mirror X mirror Y icon enable or disable; note 4 vertical or horizontal addressing; note 4 data order; note 4 bottom row swap; note 4 set Y address; 0 Y 9 set X address; 0 X 127
X
set X max; 0 X 127 Product specification
PCF8811 PCF8811
X X X X
0 0 0 0
0 0 0 0
set initial display line; 0 L 79; note 5 set start row; 0 C 79; note 6
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2004 May 17 2004 May 17 28 28 Philips Semiconductors COMMAND BYTE D/C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 1 X 0 1 VPR7 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 D7(3) DESCRIPTION D6 1 P6 0 X 0 0 VPR6 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 D5 0 P5 0 VPR5 1 0 VPR5 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 D4 0 P4 0 VPR4 0 0 VPR4 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 D3 1 P3 0 VPR3 0 0 VPR3 1 0 0 1 1 0 1 1 0 1 0 0 1 X X D2 0 P2 0 VPR2 D1 X P1 0 VPR1 X P0 1 VPR0 D0 set partial display 1 : 16 to 1 : 80 set VOP; notes 7 and 8 offset for the programming range VOP; notes 7 and 8 set VOP; note 4 switch HVgen on/off set multiplication factor set multiplication factor; note 4 set frame rate frequency; note 4 set temperature coefficient; note 4 set bias system; note 10 set manual p value; notes 4 and 11 power-save mode exit power-save mode switch internal oscillator on/off enable or disable the internal or external oscillator; note 4 enter CALMM mode reserved reserved do not use; reserved for testing Product specification
80 x 128 pixels matrix LCD driver 80 x 128 pixels matrix LCD driver
INSTRUCTION Set partial display VOP setting
EXT(2) X X 0 0 0 1 1
VOFF2 VOFF1 VOFF0 0 VPR2 PC1 1 S2 1 TC2 BS2 0 0 0 0 1 0 X X X 0 VPR1 PC0 S1 S1 FR1 TC1 BS1 1 0 0 1 1 1 X X X 1 VPR0 1 S0 S0 FR0 TC0 BS0 MP 1 1 OS EC 0 0 X X
Power control HVgen stages FR TC(9) Bias system Manual p value (p = 4) Power-save on Power-save off Internal oscillator Internal oscillator Enter CALMM mode Reserved Reserved Test
X 0 1 1 1 0 1 X X X 1 X X X X
PCF8811 PCF8811
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
Notes 1. X = don't care. 2. Philips strongly recommends that the extended command set be used. 3. D7 = MSB. 4. Commands only available with the extended command set, EXT = 1. If EXT = 0 these commands have no effect. 5. When icon mode is enabled the set initial display line is 0 L 78. 6. When icon mode is enabled the set initial row is 0 C 78. 7. Commands only used for the basic command set, EXT = 0. If EXT = 1 these commands have no effect. Care should be taken when setting VOP in the basic command set, it must be followed by another command. 13.1 13.1.1 Table 6 Explanation of the symbols COMMON INSTRUCTIONS OF THE BASIC AND EXTENDED COMMAND SET Explanation of the symbols LOGIC 0 display off normal display normal display no X mirroring no Y mirroring stop frame frequency calibration internal oscillator off display on inverse video mode all pixels on X mirroring Y mirroring LOGIC 1 0 0 0 0 0
PCF8811
8. The programming of VOP in the basic command set must be done in the following order: a) VPR[5:0] b) VOFF[2:0] c) Must be followed by another command. 9. One fixed TC is set automatically if the basic command set is used. 10. Bias system settings which can be received when the chip is used as replacement of Alth and Pleskho driving method (NOP). 11. Only for mux rates 1 : 64 and 1 : 80 the number of simultaneous rows can be manually set to p = 4.
BIT DON E DAL MX MY OC OS X[6:0] Y[3:0] Xmax[6:0] Ymax[3:0] L[6:0] C[6:0] P[6:0] PC[1:0] S[1:0]
RESET STATE
start frame frequency calibration 0 start internal oscillator 0 0000000 0000 1111111 1001 0000000 0000000 1010000 (1 : 80)/1000000 (1 : 64) 00 00
sets X address (column) for writing in the RAM sets Y address (bank) for writing in the RAM set wrap around X address (column) set wrap around Y address (bank) sets line address of the display RAM to be displayed on the initial ROW 0 sets the initial ROW 0 of the display; this command cannot access the icon driver row ROW 80; if icon row is enabled partial display mode 1 : 16 to 1 : 80; note 1 switch HV generator on/off charge pump multiplication factor
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
Note
PCF8811
1. Partial displays can be selected in steps of 8 when the icon mode is not selected. When the icon mode is selected partial displays can be selected in steps of 16. For example, without icons the available partial display sizes are 8, 16, 24, 32, 40, 48, 56, 64 or 72 lines. With icons there are 16, 32, 48 or 64 lines possible. Table 7 Power control PC[1:0] 00 01 10 11 Table 8 PSM 0 0 0 0 0 0 1 Notes 1. X = don't care. 2. The DON bit can only be addressed after DAL is activated. 3. The DAL bit has priority over the E bit. Table 9 Read status byte BIT BUSY DON RES MF[2:0] DS0 Table 10 Device recognition; note 1 DS0 0 1 Note 1. This is the only default setting after reset, another setting can be selected with the `set partial display mode' command. DESCRIPTION 64 row driver 80 row driver same bit as in Table 4 if RES = 1 a reset is in progress device manufacturer ID device recognition; see Table 10 DESCRIPTION if BUSY = 0 the chip is able to accept new commands Power-Save Mode (PSM), OS, DON, DAL and E combinations; note 1 OS 0 1 1 1 1 1 X DON X X 0 1 1 1 X DAL X 0 1 0 0 1 X E X X X 0 1 X X oscillator off; HVgen disabled oscillator on; HVgen enabled display off, ROW/COL at VSS; oscillator off; HVgen disabled; note 2 normal display mode inverse display mode all pixels on; note 3 power-save mode: display off; ROW/COL at VSS; oscillator off; HVgen disabled DESCRIPTION DESCRIPTION HVgen off HVgen on HVgen on HVgen on
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
Table 11 Multiplication settings S[1:0] 00 01 10 11 DESCRIPTION 4 x voltage multiplier 5 x voltage multiplier 6 x voltage multiplier 7 x voltage multiplier
PCF8811
DECIMAL +12 +13 +14 +15 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16
BINARY 01100 01101 01110 01111 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000
Table 12 VOS values in twos complement notation DECIMAL 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 13.1.2 BINARY 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011
SPECIFIC COMMANDS OF THE BASIC COMMAND SET
Table 13 Explanation of symbols BIT VPR[5:0] VOFF[2:0] LOGIC 0 programming value of VLCD offset for the programming value of VLCD LOGIC1 000 RESET STATE 000000
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
13.1.3 SPECIFIC COMMANDS OF THE EXTENDED COMMAND SET
PCF8811
Table 14 Explanation of symbols BIT VPR[7:6] + VPR[5:0] FR[1:0] TC[2:0] V DOR IC BRS MP(1) EC S[2:0] Note 1. It is strongly recommended to use the p = 4 setting. Table 15 Frame-rate frequency FR[1:0] 00 01 10 11 Table 16 Temperature coefficient TC[2:0] 000 001 010 011 100 101 110 111 TEMPERATURE COEFFICIENT 0 1 2 3 4 5 6 7 13.2 FRAME-RATE FREQUENCY 30 Hz 40 Hz 50 Hz 60 Hz Table 17 Multiplication settings S[2:0] 000 001 010 011 100 101 110 111 Initialization DESCRIPTION 2 x voltage multiplier 3 x voltage multiplier 4 x voltage multiplier 5 x voltage multiplier 4 x voltage multiplier 5 x voltage multiplier 6 x voltage multiplier 7 x voltage multiplier LOGIC 0 programming value of VLCD frame-rate frequency temperature coefficient horizontal addressing LSB at top no Icon row (1/16 to 1/80) bottom rows are not mirrored mux rate driven p value (automatic) use internal oscillator vertical addressing MSB at top Icon row (1/16 to 1/80) bottom rows are mirrored p = 4 selected for mux rate 1 : 64 and 1 : 80 use external oscillator LOGIC 1 11 (TC2) 010 0 0 0 0 0 0 100 RESET STATE 00000000
charge pump multiplication factor
Reset is accomplished by applying an external reset pulse (active LOW) at pad RES. When reset occurs within the specified time, all internal registers are reset, however the RAM is still undefined. The state after reset is described in Section 13.3. Pad RES must be 0.3VDD1 when VDD1 reaches VDD(min) (or higher) within a maximum time tVHRL after VDD1 goes high (see Fig.43). A reset can also be achieved by sending a reset command. This command can be used during normal operation but not to initialize the chip after power-on.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
13.3 13.3.1 Reset function BASIC COMMAND SET * Power-save mode is on * Horizontal addressing enabled (V = 0) * No data order swap (DOR = 0) * No bottom row swap (BRS = 0) * Internal oscillator enabled (EC = 0) * No frame calibration running (OC = 0). 13.4 Power-save mode
PCF8811
After reset the LCD driver has the following state: * Display setting E = 0 and DAL = 0 * Address commands X[6:0] = 0 and Y[3:0] = 0 * VLCD is equal to 0, the HV generator is switched off (PC[1:0] = 00) * No offset of the programming range (VOFF[2:0] = 0) * HV generator programming (VPR[5:0] = 0) * 4 x voltage multiplier (S[1:0] = 00) * After power-on, RAM data is undefined, the reset signal does not change the content of the RAM * All LCD outputs at VSS (display off) * Initial display line set to line 0 (L[6:0] = 0) * Initial row set to ROW 0 (C[6:0] = 0) * Full display selected (P[6:0] = mux 1 : 80 or 1 : 64) * Display is not mirrored (MX = 0 and MY = 0) * Internal oscillator is off * Power-save mode is on * No frame calibration is running. 13.3.2 EXTENDED COMMAND SET
In the power-save mode the LCD driver has the following state: * All LCD outputs at VSS (display off) * Bias generator and VLCD generator switched off; external VLCD can be disconnected * Oscillator off (external clock possible) * RAM contents not cleared; RAM data can be written * VLCD discharged to VSS in Power-down mode. There are two ways to put the chip into power-save mode: * The display must be off (DON = 0) and all the pixels on (DAL = 1) * The power-save mode command is activated. 13.5 Display control
After reset the LCD driver has the following state: * Display settings E = 0 and DAL = 0 * Icons disabled (IC = 0) * Address counter X[6:0] = 0 and Y[3:0] = 0 * Temperature control mode TC2 (TC[2:0] = 010) * VLCD is equal to 0; the HV generator is switched off (PC[1:0] = 0) * HV generator programming (VPR[7:0] = 0) * 4 x voltage multiplier (S[2:0] = 100) * Frame-rate frequency (FR[1:0] = 11) * After power-on, RAM data is undefined, the reset signal does not change the content of the RAM * All LCD outputs at VSS (display off) * Full display selected (P[6:0] = mux 1 : 80 or 1 : 64) * Initial display line set to line 0 (L[6:0] = 0) * Initial row set to ROW 0 (C[6:0] = 0) * Display is not mirrored (MX = 0; MY = 0) * Internal oscillator is off
The bits DON, E and DAL select the display mode; see Table 8. 13.5.1 MX
When MX = 0 the display RAM is written from left to right (X = 0 is on the left side and X = X max is on the right side of the display). When MX = 1 the display RAM is written from right to left (X = 0 is on the right side and X = X max is on the left side of the display). The MX bit has an impact on the way the RAM is written to. So if a horizontal mirroring of the display is desired, the RAM must first be rewritten, after changing the MX bit. 13.5.2 MY
When MY = 1, the display is mirrored vertically. A change of this bit has an immediate effect on the display.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
13.6 Set Y address of RAM 13.8 Set display start line
PCF8811
Y[3:0] defines the Y address of the display RAM. Table 18 X/Y address range Y3 0 0 0 0 0 0 0 0 1 1 Y2 0 0 0 0 1 1 1 1 0 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 0 1 0 1 CONTENT bank 0 (display RAM) bank 1 (display RAM) bank 2 (display RAM) bank 3 (display RAM) bank 4 (display RAM) bank 5 (display RAM) bank 6 (display RAM) bank 7 (display RAM) bank 8 (display RAM) bank 9 (display RAM) ALLOWED X RANGE 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127 0 to 127
L[6:0] is used to select the display line address of the display RAM to be displayed on the initial row, ROW 0. The selection of L is limited to steps of 8. When the icon row is selected, the selection of L is limited to steps of 16. When a partial mode is selected, the selection of L is also limited in steps. In addition, the selection of L = 72 is not allowed when the icon row is enabled or disabled. The initial row can, in turn, be set by C[6:0]. ROW 0 cannot be set to the icon row ROW 79 when enabled. An example of the mapping from the RAM content to the display is illustrated in Fig.30. The content of the RAM is not modified. This feature allows, for instance, screen scrolling without rewriting the RAM.
When the icon row is enabled this icon row (ROW 79) will always be in bank 9 independent of the mux rate which is programmed. 13.7 Set X address of RAM
The X address points to the columns. The range of X is 0 to 127 (7FH).
2004 May 17
34
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
set initial display line and start row when MY = 0 RAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31
X address
Display
0
L=8
1
C = 16
2
3
8
9
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
ROW 64 ROW 65 ROW 66 ROW 67 ROW 68 ROW 69 ROW 70 ROW 71 ROW 72 ROW 73 ROW 74 ROW 75 ROW 76 ROW 77 ROW 78 ROW 79
MGW751
Fig.30 Programming the L address and C address when MY = 0.
2004 May 17
35
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
13.9 Bias levels
PCF8811
The bias levels for an MRA driving method with p = 8 are given in Fig.31 when Gmax and F have the same value. The value p defines the number of rows which are simultaneously selected.
handbook, full pagewidth
VLCD V3_H V2_H V1_H VC V1_L V2_L V3_L VSS
MGW752
G max = F = VLCD 0.75G max 0.50G max 0.25G max VC -0.75G max -0.50G max -0.25G max -G max = F = VSS
Fig.31 Bias levels for a MRA system with p = 8 and Gmax = F.
The row voltage F depends on the mux rate selected (number of rows N), the threshold voltage of the liquid (VTH), the number of simultaneously selected rows (p) and the multiplexibility (m): N m m - N 1 F = ------ x V TH x --- x ------------------------------2 m-1 p (1)
The column voltages are situated around the common level VC. The column voltage levels are equidistant from each other. In Table 19 the column voltage levels are given as a function of F.
2004 May 17
36
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
Table 19 Bias levels for MRA driving method SYMBOL F = Gmax VLCD V3_H F F ( p - 2 ) x --------------------------------m- m-N F ( p - 4 ) x --------------------------------m- m-N F ( p - 6 ) x --------------------------------m- m-N 0 F - ( p - 6 ) x --------------------------------m- m-N F - ( p - 4 ) x --------------------------------m- m-N F - ( p - 2 ) x --------------------------------m- m-N -F VLCD BIAS VOLTAGES
PCF8811
DC SHIFTED BIAS VOLTAGES
V LCD (p - 2) ------------- x 1 + --------------------------------- 2 m - m - N V LCD (p - 4) ------------- x 1 + --------------------------------- 2 m - m - N V LCD (p - 6) ------------- x 1 + --------------------------------- 2 m - m - N
1/ 2VLCD
V2_H
V1_H
VC V1_L
V LCD (p - 6) ------------- x 1 - --------------------------------- 2 m - m - N V LCD (p - 4) ------------- x 1 - --------------------------------- 2 m - m - N V LCD (p - 2) ------------- x 1 - --------------------------------- 2 m - m - N VSS
V2_L
V3_L
VSS
The row voltages (F) are not necessarily larger then the column voltages. This depends on the number of rows which are selected, the multiplexibility and the value of p. However, the PCF8811 is designed in such a way that the maximum column voltages are always equal to the row voltages. In Table 20 the VLCD and the different bias levels are given for the PCF8811. The VLCD voltage is defined as: V LCD = 2 x F Where F is defined in (1) The bias system settings for different display modes are given in Table 20. All bias levels can be calculated by using the third column of Table 19 and the variables given in Table 20. Programming of the bias levels is not necessary in the PCF8811. The selection of the appropriate bias level voltages for each display mode is done automatically. Only the appropriate VLCD voltage must be programmed according to equations (1) and (2) for the display modes listed in Table 20. The variables for calculating VLCD, when the icon row is enabled, are given in Table 21. The icon row can only be addressed in the extended command set. The PCF8811 allows the value of p, for certain mux rates, to be chosen manually. 2004 May 17 37 (2)
This is only possible for the mux rates 1 : 64 and 1 : 80. If other mux rates are chosen the PCF8811 determines the optimum value of p. By setting the value of p manually a compromise can be made between contrast and power consumption with certain liquids for the high mux rates 1 : 64 and 1 : 80. However, care must be taken that the liquid which is chosen ensures that the row voltages (F) and the maximum column voltages are equal. Table 20 Relationship between mux rates and bias setting variables without icon row MUX RATE 1 : 16 1 : 24 1 : 32 1 : 40 1 : 48 1 : 56 1 : 64 1 : 72 1 : 80 N 16 24 32 40 48 56 64 72 80 m 25 49 81 49 64 81 64 81 81 p 2 2 2 4 4 4 8 8 8
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
Table 21 Relationship between mux rates and bias setting variables with the icon row (only extended command set) MUX RATE 1 : 16 1 : 32 1 : 48 1 : 64 1 : 80 13.10 Set VOP value For mux rate 1 : 80 the optimum operation voltage of a liquid can be calculated with the variables given in Table 21 and equations (1) and (2). 80 81 - 81 - 80 2 V LCD = ------ x V TH x ----- x --------------------------------------- = 4.472 x V TH 2 81 - 1 8 Where VTH is the threshold voltage of the liquid crystal material used. The way of programming the VOP value is implemented differently in the basic command set in comparison to the extended command set. In the basic command set two commands are sent to the PCF8811: namely VPR[5:0] and VOFF[2:0]. In the extended command set only one command VPR[7:0] is sent to the PCF8811. This VOP programming is illustrated in Fig.32. The programming of VOP in the basic command set can be used when the PCF8811 is used as a replacement for an IAPT LCD driver. A conversion table (ROM) can be provided which transfers the programming of an IAPT VOP value to a MRA VOP value. (3) N 24 40 56 80 80 m 49 49 81 81 81 p 2 4 8 8 8
EXT = handbook, full pagewidth1 EXT = 0
VPR [7:0] MMVOPCAL [4:0] VPR [5:0] VOFF [2:0] EXT 1 VLCD 0 LOOK-UP TABLE rom_add[8:0] ROM VOP [7:0]
MGW753
VOS [4:0]
b
a
76543210210
Fig.32 Setting of VOP in the basic and extended command set.
2004 May 17
38
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
13.10.1 BASIC COMMAND SET The VLCD at T = TCUT in the basic command set is determined by the conversion in the ROM look-up table with the programmed values of VPR[5:0] and VOFF[2:0]. It can, additionally, be adjusted with the VLCD offset pads VOS[4:0] to obtain the optimum optical performance. Instead of using the VLCD offset pads (VOP[4:0]) the VLCD can be adjusted with the module maker calibration setting MMVOPCAL[4:0]; see Chapter 22. (4) V LCD ( T = T ) = a + ( V OS [4:0] + V OP [7:0] ) x b
CUT
PCF8811
Instead of using the VLCD offset pads (VOP[4:0]) the VLCD can be adjusted with the module maker calibration setting MMVOPCAL[4:0]; see Chapter 22. (5) V LCD ( T = T ) = a + ( V OS [4:0] + V PR [7:0] ) x b
CUT
Where: * TCUT is a reference temperature (see Section 13.11) * a is a fixed constant value (see Table 22) * b is a fixed constant value (see Table 22) * VPR[7:0] is the programmed VOP value * VOS[4:0]/MMVOPCAL[4:0] is the value of the offset VLCD offset pads or the value stored in the OTP cells. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9 V) the user has to ensure while setting the VPR register and selecting the Temperature Compensation (TC), that under all conditions and including all tolerances the VLCD remains below 9.0 V. This is valid for the two different command sets.
Where: * TCUT is a reference temperature; see Section 13.11 * a is a fixed constant value; see Table 22 * b is a fixed constant value; see Table 22 * VOP[7:0] is the result of the conversion table * VOS[4:0]/MMVOPCAL[4:0] is the value of the offset VLCD offset pads or the value stored in the OTP cells. Table 22 Parameters of VLCD for the basic and extended command set SYMBOL TCUT b a VALUE 40 0.03 3 UNIT C V V
13.10.2 EXTENDED COMMAND SET The VLCD at T = TCUT can be calculated with equation (5). In the extended command set VPR[7:0] is the same value as VOP[7:0]. It can additionally be adjusted with the VLCD offset pads VOS[4:0] to obtain the optimum optical performance.
2004 May 17
39
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
MGT847
V LCD
b
a
00
01
02
03
04
05
06
...
...
FD
FE
FF
V OP
VOP[7:0] programming, (00H to FFH).
Fig.33 VLCD programming of PCF8811.
13.11 Temperature control Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage VLCD might have to be increased at lower temperature to maintain optimum contrast. The VLCD at a specific temperature is calculated as follows for both command sets. VLCD (at T = TCUT) is given by equations (4) or (5), depending on the command set which is used. (6) V LCD = V LCD x [ 1 + ( T - T CUT ) x TC ]
(T) ( T = T CUT )
handbook, halfpage
VLCD
MGW754
In the extended command set and basic command set 8 different temperature coefficients are available (see Fig.34). The typical values of the different temperature coefficients are given in Chapter 16. The coefficients are proportional to the programmed VLCD. The basic and extended command set differ in the way that the temperature coefficients can be accessed. In the basic command set only one temperature coefficient is available. However, the possibility exists to program the default temperature coefficient by means of OTP programming; see Chapter 22. In the extended command set the different temperature coefficients are selected by the interface with three bits TC[2:0].
TCUT
T
Fig.34 Temperature coefficients.
2004 May 17
40
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2. SYMBOL VDD1 VDD2, VDD3 VLCD Vi ISS Ii, Io Ptot Pout Tstg Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. general supply voltage supply voltage for the internal voltage generator LCD supply voltage all input voltages ground supply current DC input or output current total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 -0.5 -0.5 -0.5 -50 -10 - - -65
PCF8811
MAX. +6.5 +4.5 +10.0 +50 +10 300 30 +150 V V V
UNIT
VDD1 + 0.5 V mA mA mW mW C
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. 15 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
2004 May 17
41
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
16 DC CHARACTERISTICS VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = 3.0 V to 9.0 V; Tamb = -40 C to +85 C; unless otherwise specified. SYMBOL VDD1 PARAMETER general supply voltage basic command set; when using ROM look-up table (see Section 13.10) VDD2, VDD3 VLCDIN supply voltage for the internal voltage generator LCD supply voltage LCD voltage externally supplied (voltage generator disabled) CONDITIONS MIN. 1.7 2.0 - - TYP. MAX. 3.3 3.3 UNIT V V
1.8 -
- -
3.3 9.0
V V
VLCDOUT
voltage multiplier output voltage tolerance of generated VLCD general supply current supply current for the internal voltage generator total supply current (VDD1 + VDD2 + VDD3)
LCD voltage internally - generated (voltage generator enabled); note 1 without calibration with calibration; note 2 notes 3 and 4 notes 4 and 5 notes 3 and 4 notes 5 and 4 notes 5 and 4 -300 -70 0.5 15 0 130 145
-
9.0
V
VLCD(tol) IDD1 IDD2, IDD3 IDD(tot)
- - 1.5 25 0.5 150 175
+300 +70 5 50 1 200 250
mV mV A A A A A
Logic inputs; MF[2:0], VOS[4:0], DS0, EXT, PS[2:0], RES and OSC VIL VIH IL Rcol Rrow Vbias(col) Vbias(row) LOW-level input voltage HIGH-level input voltage leakage current VI = VDD or VSS VLCD = 5 V VLCD = 5 V VSS -1 - - -100 -100 - - - - 0 0 0.2VDD1 V VDD1 +1 V A k k mV mV 0.8VDD1 -
Column and row outputs column output resistance COL 0 to COL 127 row output resistance ROW 0 to ROW 79 bias tolerance voltage COL 0 to COL 127 bias tolerance voltage ROW 0 to ROW 80 5 5 +100 +100
LCD supply voltage generator TC0 TC1 TC2 TC3 TC4 TC5 VLCD temperature coefficient 0 VLCD temperature coefficient 1 VLCD temperature coefficient 2 VLCD temperature coefficient 3 VLCD temperature coefficient 4 VLCD temperature coefficient 5 - - - - - - 0 -0.16 x 10-3 -0.33 x 10-3 -0.50 x -0.66 x 10-3 10-3 - - - - - /C /C /C /C /C /C
-0.833 x 10-3 -
2004 May 17
42
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
SYMBOL TC6 TC7
PARAMETER VLCD temperature coefficient 6 VLCD temperature coefficient 7 note 6
CONDITIONS - -
MIN.
TYP. -1.25 x -1.66 x - 10-3 10-3 - -
MAX.
UNIT /C /C
Parallel interface; VDD1 = 1.8 V to 3.3 V VIL VIH LOW-level input voltage HIGH-level input voltage VSS 0.2VDD1 V VDD1 V 0.8VDD1 - -
Serial interface; VDD1 = 1.7 V to 3.3 V VIL VIH LOW-level input voltage HIGH-level input voltage VSS 0.2VDD1 V VDD1 V 0.8VDD1 - - - VSS - - -
I2C-bus interface; VDD1 = 1.8 V to 3.3 V IOL(SDA) VIL VIH VOL VOH Notes 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Valid for values of temperature, VPR and TC used at calibration. 3. During power-down all static currents are switched off. 4. Conditions are: VDD1 = 1.8 V, VDD2 = 2.7 V, VLCD = 8.05 V, voltage multiplier 4VDD2, inputs at VDD1 or VSS, interface inactive, internal VLCD generation, VLCD output is loaded by 10 A and Tamb = 25 C. 5. Normal mode. 6. TC7 can only be used when VDD2 = VDD3 = 2.4 V or higher. 17 AC CHARACTERISTICS VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = -40 C to +85 C; note 1; unless otherwise specified. SYMBOL fext fframe tVHRL tRW Notes 1. All specified timings are based on 20 % and 80 % of VDD. 2. RES may be LOW before VDD goes HIGH. PARAMETER external clock frequency frame frequency VDD to RES LOW RES LOW pulse width Tamb = 25 C; VDD1 = 2.4 V see Fig.43 see Fig.43 CONDITIONS - 54 43 0(2) 500 MIN. TYP. 200 60 58 - - - 66 73 1 - MAX. UNIT kHz Hz Hz s ns LOW-level output current at pin SDA LOW-level input voltage HIGH-level input voltage VOL = 0.4 V; VDD1 > 2 V VOL = 0.2VDD1; VDD1 < 2 V 3 2 VDD1 mA mA V
0.3VDD1 V
0.7VDD1 - IOL = 0.5 mA IOH = -0.5 mA VSS -
Output levels for all interfaces LOW-level output voltage HIGH-level output voltage 0.2VDD1 V VDD1 V 0.8VDD1 -
2004 May 17
43
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
18 PARALLEL INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = -40 C to +85 C; unless otherwise specified. SYMBOL PARAMETER MIN. MAX. UNIT
Parallel bus timing; see Figs 35 and 36 6800 SERIES tSU;DC tHD;DC Tcyc(DS) tDS(L) tDS(H) tSU;RW tHD;RW tSU;CE tHD;CE tSU;DAT tHD;DAT tDAT;ACC tDAT;OH data/command set-up time data/command hold time data strobe cycle time data strobe LOW time data strobe HIGH time read/write set-up time read/write hold time chip enable set-up time chip enable hold time data set-up time data hold time data output access time data output disable time 40 20 1000 320 300 280 20 280 0 20 40 - - - - - - - - - - - - - 280 20 ns ns ns ns ns ns ns ns ns ns ns ns ns
2004 May 17
44
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
RW t SU;CE t SU;RW t HD;CE t HD;RW
D/C t SU;DC SCE t HD;DC
Tcyc(DS) t DS(H) t DS(L)
E t SU;DAT t HD;DAT D0 to D7 (write) t DAT;ACC D0 to D7 (read)
MGW755
t DAT;OH
Fig.35 Parallel interface timing (6800-series) (read).
2004 May 17
45
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
D/C, RW t SU;RW t HD;RW
D/C t SU;DC E Tcyc(DS) t DS(L) t DS(H) t HD;DC
SCE t SU;DAT
t HD;DAT
D0 to D7 (Write) t DAT;ACC D0 to D7 (Read)
MGW756
t DAT;OH
Fig.36 Parallel interface timing (6800-series) (write).
2004 May 17
46
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
19 SERIAL INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = -40 C to +85 C; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - - - 50 50 - 100 30 500 MAX. UNIT
3-line and 4-line (SPI and serial interface); see Fig.37 to Fig.40 fSCLK Tcyc tPWH1 tPWL1 tS2 tH2 tPWH2 tH5 tS4 tH4 tS3 tH3 tS1 tH1 t1 t2 t3 t4 Cb Rb Notes 1. All specified timings are based on 20 % and 80 % of VDD. 2. tH5 is the time from the previous SCLK rising edge (irrespective of the state of SCE) to the falling edge of SCE. 3. SDOUT disable time for SPI 3-line or 4-line interface. 4. SDOUT disable time for serial interface 3-line. 5. Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance + printed-circuit board. clock frequency clock cycle SCLK SCLK pulse width HIGH SCLK pulse width LOW SCE set-up time SCE hold time SCE minimum high time SCE start hold time SDIN set-up time SDIN hold time data/command set-up time data/command hold time SDIN set-up time SDIN hold time SDOUT access time SDOUT disable time SCE hold time SDOUT disable time capacitive load for SDO series resistance for SDO note 4 note 5 note 5 note 3 note 2 9.00 111 45 45 50 45 50 50 50 50 50 50 50 50 - - 50 25 - - MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
2004 May 17
47
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
t S2
t H2
t PWH2
SCE (t H5 ) T cyc t PWL1 SCLK t PWH1 t S2 t H5
t S1 SDATA
t H1
MGW757
Fig.37 3-line serial interface timing.
handbook, full pagewidth
t S2
t H2
t PWH2
SCE t S3 D/C T cyc t PWL1 SCLK t PWH1 t S2 t H3 (t H5 ) t H5
t S4 SDATA
t H4
MGW758
Fig.38 4-line serial interface timing.
2004 May 17
48
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
SCE t3 SCLK t H1 SDATA t S1
t1 SDOUT
t2
MGW759
Fig.39 Serial interface timing; read mode SPI 3- or 4-line.
handbook, full pagewidth
SCE t3 SCLK t H1 SDATA t S1
t1 SDOUT
t4
MGW760
Fig.40 Serial interface timing; read mode serial interface 3-line.
2004 May 17
49
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
20 I2C-BUS INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = -40 C to +85 C; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. - - - - - - - - - - - - - - MAX. UNIT
Fs-mode; see Fig.41 fSCLH tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STO tSP tBUF VnL SCLH clock frequency set-up time (repeated) START condition hold time (repeated) START condition LOW period of the SCLH clock HIGH period of the SCLH clock data set-up time data hold time SCL and SDA rise time SCL and SDA fall time capacitive load represented by each bus line set-up time for STOP condition tolerable spike width on bus bus free time between START and STOP condition noise margin at the LOW level for each connected device (including hysteresis) noise margin at the HIGH-level for each connected device (including hysteresis) note 2 note 2 0 600 600 1300 600 100 0 20 + 0.1Cb 20 + 0.1Cb - 600 - 1300 0.1VDD1 400 - - - - - 900 300 300 400 - 50 - - kHz ns ns ns ns ns ns ns ns pF ns ns ns V
VnH
0.2VDD1
-
-
V
Hs-mode; see Fig.42 fSCLH tSU;STA tHD;STA tLOW tHIGH tSU;DAT tHD;DAT trCL trCL1 tfCL trDA tfCL1 SCLH clock frequency set-up time (repeated) START condition hold time (repeated) START condition LOW period of the SCLH clock HIGH period of the SCLH clock data set-up time data hold time rise time of the SCLH signal rise time of the SCLH signal after the acknowledge bit fall time of the SCLH signal rise time of the SDAH signal fall time of the SCLH signal 0 160 160 160 60 10 20 10 10 10 10 10 - - - - - - - - - - - - 3.4 - - - - - 70 40 80 40 80 80 MHz ns ns ns ns ns ns ns ns ns ns ns
2004 May 17
50
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
SYMBOL tSU;STO Cb2 Cb
PARAMETER set-up time for STOP condition capacitive load for the SDAH and SCLH lines capacitive load for the SDAH + SDA line and SCLH + SCL line tolerable spike width on bus noise margin at the LOW-level for each connected device (including hysteresis) noise margin at the HIGH-level for each connected device (including hysteresis) note 2 note 2
CONDITIONS 160 - -
MIN.
TYP. - - -
MAX. - 100 400
UNIT ns pF pF
tSP VnL
- 0.1VDD1
- -
5 -
ns V
VnH
0.2VDD1
-
-
V
Notes 1. All specified output timings are based on 20 % and 80 % of VDD1. 2. Cb = 100 pF total capacitance of one bus line.
handbook, full pagewidth
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA tSU;STA tSU;STO
S
tHD;DAT
tHIGH
Sr
P
S
MSC610
S = Start. Sr = Start repeated. P = Stop.
Fig.41 I2C-bus timing diagram (Fs-mode).
2004 May 17
51
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
Sr tfDA
trDA
Sr
P
SDAH
tSU;STA
tHD;DAT tHD;STA tSU;DAT
tSU;STO
SCLH tfCL trCL1
(1)
trCL tHIGH tLOW tLOW tHIGH
trCL1
(1)
MGK871
= MCS current source pull-up = Rp resistor pull-up
(1) Rising edge of the first SCLH clock pulse after an acknowledge bit.
Fig.42 I2C-bus timing diagram (Hs-mode).
handbook, full pagewidth
VDD t RW RES t RW
VDD t VHRL t RW t RW
RES
MGW761
Fig.43 Reset timing.
2004 May 17
52
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
21 APPLICATION INFORMATION
PCF8811
Semiconductors are light sensitive. Exposure to light sources can cause malfunction of the IC. In the application it is therefore required to protect the IC from light. The protection has to be done on all sides of the IC, i.e. front, rear and all edges. The pinning of the PCF8811 has an optimum design for single plane wiring e.g. for chip-on-glass display modules. Display size: 80 x 128 pixels. For further application information refer to Philips Application note AN10170.
handbook, full pagewidth
DISPLAY 80 x 128 pixels
PCF8811
VDD2 VDD1 VSS1 VSS2 CVDD VDD VSS
CVLCD I/O
MGW762
Fig.44 Application diagram: internal charge pump is used and a single supply.
handbook, full pagewidth
DISPLAY 80 x 128 pixels
PCF8811
VDD2 VDD1 VSS1 VSS2 CVDD2 VDD2 VSS
C VDD1 VDD1 I/O
CVLCD
MGW763
Fig.45 Application diagram: internal charge pump is used and two separate supplies (VDD1 and VDD2).
2004 May 17
53
VLCDSENSE VLCDOUT VLCDIN
VLCDSENSE VLCDOUT VLCDIN
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
DISPLAY 80 x 128 pixels
PCF8811
VDD2 VDD1 VSS1 VSS2 CVDD VDD VSS
I/O
VLCDSENSE VLCDOUT VLCDIN VLCDIN
MGW764
Fig.46 Application diagram: external high voltage is used.
The required minimum value for the external capacitors in an application with the PCF8811 are: CVLCD = 1 F to 4.7 F depending on the application CVDD, CVDD1 and CVDD2 = 1 F. For these capacitors higher values can be used.
2004 May 17
54
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
22 MODULE MAKER PROGRAMMING The One Time Programmable (OTP) technology is implemented on the PCF8811. It enables the module maker to program some extended features of the PCF8811 after it has been assembled on an LCD module. Programming is made under the control of the interfaces and the use of one special pin. This pin must be made available on the module glass but need not to be accessed by the set maker. The PCF8811 features 3 module maker programmable parameters: * VLCD calibration * Temperature coefficient selection * Seal bit. 22.1 VLCD calibration
PCF8811
In theory, both may be used together but it is recommended that the VOS pins are tied to VSS when OTP calibration is being used. This will set them to a default offset of zero. If both are used then the addition of the two 5-bit numbers must not exceed a 5-bit result otherwise the resultant value will be undefined. The final adder in the circuit has underflow and overflow protection. In the event of an overflow, the output will be clamped to 255; during an underflow the output will be clamped to 0. The final control to the high voltage generator, VOP, will be the sum of all the calibration registers and pins. The VLCD equation (4) or (5) given in Section 13.10 must be extended to include the OTP calibration, as follows; (7) V LCD ( T = T ) = a + ( V OS [4:0] + MMVOPCAL[4:0] + V OP [7:0] ) x b
CUT
The first feature included is the ability to adjust the VLCD voltage with a 5-bit code (MMVOPCAL). This code is implemented in twos complement notation giving rise to a positive or negative offset to the VPR register. This is in the same manner as the on-glass calibration pins VOS.
The possible MMVOPCAL[4:0] values are the same as the VOS[4:0] values; see Table 12.
handbook, full pagewidth
OTP VLCD calibration: 5-bit offset
range -16 to +15
MMVOPCAL[4:0] laser trim pins: 5-bit offset VOS[4:0] range -16 to +15
+ +
VOP [7:0] range: 0 to +255 to high voltage generator
range 0 to +255 usable range +32 to +255 VPR register: 8-bit value VPR [7:0]
MGU287
Fig.47 VLCD calibration.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
22.2 Temperature coefficient selection
PCF8811
This OTP architecture allows the following operations: 1. Reading data from the OTP cells. The content of the non-volatile OTP cells is transferred to the shift register where upon it may affect the PCF8811 operation. 2. Writing data to the OTP cells. First, all 9 bits of data are shifted into the shift register via the interface. The content of the shift register is then transferred to the OTP cells (there are some limitations related to storing data in these cells; see Section 22.7). 3. Checking calibration without writing to the OTP cells. Shifting data into the shift register allows the effects on the VLCD voltage to be observed. The reading of data from the OTP cells is initiated by either: * Exit from power-save mode * The `Refresh' command (power control). It should be noted that in both cases the reading operation needs up to 5 ms to complete. The shifting of data into the shift register is performed in the special mode CALMM. In the PCF8811 the CALMM mode is entered by the CALMM command. Once in the CALMM mode the data is shifted into the shift register via the interface at the rate of 1-bit per command. After transmitting the last (9th) bit and exiting the CALMM mode, the serial interface will return to the normal mode and all other commands can be sent. Care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the CALMM mode, otherwise the bits will be in the wrong positions. In the shift register the value of the seal bit is, like the others, always zero at reset. To ensure that the security feature works correctly, the CALMM command is disabled until a refresh has been performed. Once the refresh is completed, the seal bit value in the shift register will be valid and permission to enter the CALMM mode can thus be determined. The 9 bits are shifted into the shift register in a predefined order: first 5 bits of MMVOPCAL[4:0], 3 bits for MMTC[2:0] and lastly the seal bit. The MSB is always first, thus the first bit shifted is MMVOPCAL[4] and the two last bits are MMTC[0] and the seal bit.
The second feature is an OTP factory default setting for the temperature coefficient selection (MMTC) in the basic command set. This 3-bit value will be loaded from OTP after leaving the power-save mode or by the refresh command. The idea of this feature is to provide, in the basic command set, the complete set of temperature coefficients without an additional command. In the extended command set the temperature coefficient can be programmed as given in Table 16. 22.3 Seal bit
The module maker programming is performed in a special mode: the calibration mode (CALMM). This mode is entered via a special interface command, CALMM. To prevent wrongful programming, a seal bit has been implemented which prevents the device from entering the calibration mode. This seal bit, once programmed, can not be reversed, thus further changes in programmed values are not possible. Applying the programming voltages when not in CALMM mode will have no effect on the programmed values. Table 23 Seal bit definition SEAL BIT 0 1 22.4 ACTION possible to enter calibration mode calibration mode disabled
OTP architecture
The OTP circuitry in the PCF8811 contains 9 bits of data: 5 for VLCD calibration (MMVOPCAL), 3 for the temperature coefficient default setting in the basic command set MMTC and 1 seal bit. The circuitry for 1-bit is called an OTP slice. Each OTP slice consists of 2 main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are only accessible through their shift register cells: on the one hand both reading from and writing to the OTP cells is performed with the shift register cells, on the other hand only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Fig.48.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
DATA TO THE CIRCUIT FOR CONFIGURATION AND CALIBRATION OTP slice
SHIFT REGISTER FLIP-FLOP
SHIFT REGISTER DATA INPUT
SHIFT REGISTER
read data from the OTP cell
write data to the OTP cell
OTP CELLs
MGU289
OTP CELL
Fig.48 Basic OTP architecture.
22.5
Interface commands
These instructions are in addition to those indicated in Table 5. Table 24 Additional instructions; note 1 COMMAND BYTE NAME CALMM Power control (`Refresh') Note 1. X = don't care. 22.5.1 CALMM EXT X X D/C 0 0 R/W D7 0 0 1 0 D6 0 0 D5 0 1 D4 0 0 D3 0 1 D2 0 PC1 D1 1 PC0 D0 0 1 enter CALMM mode switch HVgen on/off to force a refresh of the shift register ACTION
This instruction puts the device in calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode all commands are interpreted as shift register data. The mode can only be exited by sending data with bit D7 set to logic 0. Reset will also clear this mode. Each shift register data byte is preceded by D/C = 0 and has only 2 significant bits, thus the remaining 6 bits are ignored. Bit D7 is the continuation bit (D7 = 1 remain in CALMM mode, D7 = 0 exit CALMM mode). Bit D0 is the data bit and its value is shifted into the OTP shift register (on the falling edge of SCLK).
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
22.5.2 REFRESH
PCF8811
It is assumed that the PCF8811 has just been reset. After transmitting the last bit the PCF8811 can exit or remain in the CALMM mode (see step 1). It should be noted that while in CALMM mode the interface does not recognize commands in the normal sense. After this sequence has been applied it is possible to observe the impact of the data shifted in. The described sequence is, however, not useful for OTP programming because the number of bits with the value logic 1 is greater than that allowed for programming; see Section 22.7. Figure 49 shows the shift register after this action.
The action of the `Refresh' instruction is to force the OTP shift register to re-load from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all other instructions may be sent. In the PCF8811 the `Refresh' instruction is associated with the `Power control' instruction so that the shift register is automatically refreshed every time the high voltage generator is enabled or disabled. It should be noted however, that if this instruction is sent while in the power-save mode, the PC[1:0] bits will be updated but the refreshing will be ignored. 22.6 Example of filling the shift register
An example of the sequence of commands and data is shown in Table 25. In this example the shift register is filled with the following data: MMVOPCAL = -4 (11100 BIN), MMTC = 2 (010 BIN) and the seal bit is 0. Table 25 Example sequence for filling the shift register; note 1 STEP 1 2 3 4 5 6 7 8 9 10 11 12 13 Notes 1. X = don't care. 2. The data for the bits is not in the correct shift register position until all bits have been sent. X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 X X X X X X X X X X 0 X X X X X X X X X X 0 X X X X X X X X X X 0 X X X X X X X X X X 0 X X X X X X X X X X 1 X X X X X X X X X X 0 1 1 1 0 0 0 1 0 0 0 EXT X D/C 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 ACTION exit Power-down wait 5 ms for refresh to take effect enter CALMM mode shift in data. MMVOPCAL[4] is first bit; note 2 MMVOPCAL[3] MMVOPCAL[2] MMVOPCAL[1] MMVOPCAL[0] MMTC[2] MMTC[1] MMTC[0] seal bit; exit CALMM mode seal bit; remain in CALMM mode
An alternative ending could be to stay in CALMM mode
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
handbook, full pagewidth
OTP SHIFT REGISTER shifting direction SEAL BIT = 0
LSB MMTC [2:0] MSB LSB
MMVOPCAL [4:0] 0 1 1
MSB
0
1
0
0
1
MGW765
Fig.49 Shift register contents after example sequence of Table 25.
22.7
Programming flow
Programming is achieved whilst in CALMM mode and with the application of the programming voltages. As mentioned previously, the data for programming the OTP cell is contained in the corresponding shift register cell. The shift register cell must be loaded with a logic 1 in order to program the corresponding OTP cell. If the shift register cell contains a logic 0, then no action will take place when the programming voltages are applied. Once programmed, an OTP cell cannot be de-programmed. An already programmed cell, i.e. an OTP cell containing a logic 1, must not be re-programmed. During programming a substantial current flows in the VLCDIN pin. For this reason it is recommended to program only one OTP cell at a time. This is achieved by filling all but one shift register cells with logic 0.
It should be noted that the programming specification refers to the voltages at the chip pins, contact resistance must therefore be considered by the user. An example sequence of commands and data for OTP programming is given in Table 26. The order for programming cells is not significant. However, it is recommended that the seal bit is programmed last. Once this bit has been programmed it will not be possible to re-enter the CALMM mode. It is assumed that the PCF8811 has just been reset.
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59
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
Table 26 Sequence for OTP programming; note 1 STEP EXT 1 2 3 4 5 6 7 9 10 11 12 13 14 15 X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 X X X X X X X X X 0 0 X X X X X X X X X 1 0 X X X X X X X X X 0 0 X X X X X X X X X 0 1 X X X X X X X X X 1 0 1 1 1 0 0 0 1 0 0 X D/C 0 R/W 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1
PCF8811
ACTION exit power-save wait 5 ms for refresh to take effect re-enter Power-down (DON = 0) enter CALMM mode shift in data; MMVOPCAL[4] is first bit MMVOPCAL[3] MMVOPCAL[2] MMVOPCAL[1] MMVOPCAL[0] MMTC[2] MMTC[1] MMTC[0] seal bit; remain in CALMM mode apply programming voltage at pins VOTPPROG and VLCDIN according to Section 22.8 apply external reset
Repeat steps 5 to 14 for each bit that should be programmed to 1 16 Note 1. X = don't care. 22.8 Programming specification
Table 27 Programming specification; see Fig.50 SYMBOL VOTPPROG PARAMETER voltage applied to pin VOTPPROG relative to VSS1 CONDITIONS programming active; note 1 programming inactive; note 1 VLCDIN voltage applied to pin VLCDIN relative to VSS1 programming active; notes 1 and 2 programming inactive; notes 1 and 2 ILCDIN IVOTPPROG Tamb(PROG) tSU;SCLK current drawn by VLCDIN during programming current drawn by VOTPPROG during programming ambient temperature during programming set-up time of internal data after last clock when programming a single bit to logic 1 MIN. 11.0 VSS - 0.2 9 TYP. 11.5 0 9.5 MAX. 12.0 +0.2 10 4.5 1000 200 40 - UNIT V V V V A A C s
VDD2 - 0.2 VDD2 - - 0 1 850 100 25 -
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60
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
SYMBOL tHD;SCLK tSU;VOTPPROG tHD;VOTPPROG tPW Notes
PARAMETER hold time of internal data before next clock set-up time of VOTPPROG prior to programming hold time of VOTPPROG after programming pulse width of programming voltage
CONDITIONS 1 1 1
MIN.
TYP. - - - 120
MAX. - 10 10 200
UNIT s s ms ms
100
1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee a sufficiently high voltage at the chip pins. 2. The Power-down mode (DON = 0 and DAL = 1) and CALMM mode must be active while the VLCDIN pin is being driven.
handbook, full pagewidth
tSU;SCLK
tHD;SCLK
SCLK
VVOTPPROG
VLCDIN
tSU;VOTPROG tPW
tHD;VOTPPROG
MGW766
Fig.50 Programming waveforms.
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
23 CHIP INFORMATION The PCF8811 is manufactured in n-well CMOS technology. The substrate is at VSS potential. 24 BONDING PAD LOCATIONS Table 28 Bonding pad information PAD Pad pitch Pad size (aluminium) Bump dimensions Wafer thickness (excluding bumps) ROWS/COLS SIDE min. 51.84 42.84 x 105 31.9 x 100 x 17.5 (5) 381 (25) INTERFACE SIDE min. 54 50 x 100 34 x 95 x 17.5 (5) m m m m
PCF8811
UNIT
handbook, halfpage
12.45 mm
handbook, halfpage
2.31 mm
PCF8811
pitch
y center
90 m
y
x
MGW767
x center
MGW768
Fig.51 Chip size and pad pitch.
Fig.52 Shape of alignment mark (90 m diameter).
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Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
Table 29 Bonding pad locations All x and y co-ordinates are referenced to the centre of the chip (dimensions in m; see Fig.53). CO-ORDINATES SYMBOL dummy_slanted alignment mark dummy dummy dummy dummy dummy dummy MF2 MF1 MF0 DS0 OSC EXT PS0 PS1 PS2 VSS(tie off) SDAHOUT SDAH SDAH SCLH/SCE SCLH/SCE VOTPPROG VOTPPROG VOTPPROG RES D/C R/W E VDD(tie off) DB0 DB1 DB2 DB3 PAD x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 6092 5995 5876 5822 5768 5714 5660 5390 5012 4850 4688 4526 4364 4094 3932 3770 3608 3446 2960 2420 2366 1826 1772 1664 1610 1556 1448 1232 962 800 638 476 314 152 -10 y 1030 1017 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 +1030 DB4 DB5 DB6 DB7 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 VDD3 VDD3 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2
PCF8811
CO-ORDINATES SYMBOL PAD x 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 -172 -334 -550 -712 -874 -928 -982 -1036 -1090 -1144 -1198 -1252 -1306 -1360 -1414 -1468 -1522 -1576 -1630 -1684 -1738 -1792 -1846 -1900 -1954 -2062 -2116 -2170 -2224 -2278 -2332 -2386 -2440 -2494 -2548 -2602 -2656 y +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030
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63
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
CO-ORDINATES SYMBOL VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 T5 T2 T1 T4 T3 VOS4 VOS3 VOS2 VOS1 VOS0 VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSENSE VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN alignment mark dummy PAD x 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 -2710 -2764 -2818 -2872 -2926 -2980 -3034 -3088 -3250 -3304 -3466 -3628 -3790 -4060 -4222 -4384 -4654 -4816 -4924 -4978 -5032 -5086 -5140 -5194 -5248 -5302 -5356 -5410 -5464 -5518 -5572 -5626 -5680 -5734 -5788 -5904 -6004 y +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1030 +1017 +1030 dummy dummy dummy dummy dummy R79 R78 R77 R76 R75 R74 R73 R72 R71 R70 R69 R68 R67 R66 R65 R64 R63 R62 R61 R60 R59 R58 R57 R56 R55 R54 R53 R52 R51 R50 R49 R48 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 SYMBOL PAD
CO-ORDINATES x -6058 -6112 -6129.24 -6077.40 -6025.56 -5973.72 -5921.88 -5870.04 -5818.20 -5766.36 -5714.52 -5662.68 -5610.84 -5559.00 -5507.16 -5455.32 -5403.48 -5351.64 -5299.80 -5247.96 -5196.12 -5144.28 -5092.44 -5040.60 -4988.76 -4936.92 -4885.08 -4833.24 -4781.40 -4729.56 -4677.72 -4625.88 -4574.04 -4522.20 -4470.36 -4418.52 -4366.68 y +1030 +1030 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5
2004 May 17
64
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
CO-ORDINATES SYMBOL R47 R46 R45 R44 R43 R42 R41 R40 R80 (duplicate R79) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 PAD x 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 -4314.84 -4263 -4211.16 -4159.32 -4107.48 -4055.64 -4003.80 -3951.96 -3900.12 -3640.92 -3589.08 -3537.24 -3485.40 -3433.56 -3381.72 -3329.88 -3278.04 -3226.20 -3174.36 -3122.52 -3070.68 -3018.84 -2967 -2915.16 -2863.32 -2811.48 -2759.64 -2707.80 -2655.96 -2604.12 -2552.28 -2500.44 -2448.60 -2396.76 -2344.92 -2293.08 -2241.24 y -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 SYMBOL PAD
CO-ORDINATES x -2189.40 -2137.56 -2085.72 -2033.88 -1878.36 -1826.52 -1774.68 -1722.84 -1671.00 -1619.16 -1567.32 -1515.48 -1463.64 -1411.80 -1359.96 -1308.12 -1256.28 -1204.44 -1152.60 -1100.76 -1048.92 -997.08 -945.24 -893.40 -841.56 -789.72 -737.88 -686.04 -634.20 -582.36 -530.52 -478.68 -426.84 -375 -323.16 -271.32 -115.80 y -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5
2004 May 17
65
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
CO-ORDINATES SYMBOL C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 PAD x 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 -63.96 -12.12 +39.72 +91.56 +143.40 +195.24 +247.08 +298.92 +350.76 +402.60 +454.44 +506.28 +558.12 +609.96 +661.80 +713.64 +765.48 +817.32 +869.16 +921.00 +972.84 +1024.68 +1076.52 +1128.36 +1180.20 +1232.04 +1283.88 +1335.72 +1387.56 +1439.40 +1491.24 +1646.76 +1698.60 +1750.44 +1802.28 +1854.12 +1905.96 y -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 SYMBOL PAD
CO-ORDINATES x +1957.80 +2009.64 +2061.48 +2113.32 +2165.16 +2217.00 +2268.84 +2320.68 +2372.52 +2424.36 +2476.20 +2528.04 +2579.88 +2631.72 +2683.56 +2735.40 +2787.24 +2839.08 +2890.92 +2942.76 +2994.60 +3046.44 +3098.28 +3150.12 +3201.96 +3253.80 +3461.16 +3513.00 +3564.84 +3616.68 +3668.52 +3720.36 +3772.20 +3824.04 +3875.88 +3927.72 +3979.56 y -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5
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66
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
CO-ORDINATES SYMBOL R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 PAD x 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 +4031.40 +4083.24 +4135.08 +4186.92 +4238.76 +4290.60 +4342.44 +4394.28 +4446.12 +4497.96 +4549.80 +4601.64 +4653.48 +4705.32 +4757.16 +4809 +4860.84 +4912.68 +4964.52 +5016.36 y -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 R31 R32 R33 R34 R35 R36 R37 R38 R39 dummy dummy dummy dummy dummy dummy dummy dummy dummy dummy 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 SYMBOL PAD
CO-ORDINATES x +5068.20 +5120.04 +5171.88 +5223.72 +5275.56 +5327.40 +5379.24 +5431.08 +5482.92 +5638.44 +5690.28 +5742.12 +5793.96 +5845.80 +5897.64 +5949.48 +6001.32 +6053.16 +6105.00 y -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5 -1032.5
2004 May 17
67
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
VLCDSENSE
VLCDOUT
VLCDIN
VDD3
VDD2
PCF8811
DB7/SDATA DB6/SCLK DB5/SDO DB4 DB3/SA1 DB2/SA0 DB1 DB0 VDD1* E/RD R/W / WR D/C RES
VOS0 VOS1 VOS2 VOS3 VOS4 T3 T4 T1 T2 T5
VOTPPROG
SCLH/SCE
SDAHOUT
SDAH
VSS1*
y
x 0,0
PS2 PS1 PS0 EXT OSC DS0 MF0 MF1 MF2
VDD1
VSS2
VSS1
mgw769
* VSS1* and VDD1* for local tie offs.
Fig.53 Bonding pad location (viewed from bump side).
2004 May 17
68
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
25 DEVICE PROTECTION DIAGRAM
PCF8811
handbook, full pagewidth
VDD1
VDD2
VDD3
VSS1
VSS1 VSS2
VSS1
VSS2
VLCDIN , VLCDSENSE
VLCDOUT
VSS1 VSS1
VSS1
VOTPPROG
VLCDIN
VDD1 DB [7:0], SCLK, SDATA, SDO, SA1, SA0, R/W, WR
VSS1
LCD outputs
VSS1
VSS1
VDD1 OSC, RES, RD, D/C, PS [2:0], T1, T2, T5, E VSS1 I2C-bus pins
VDD1
VDD1
T3, T4, VSS1*, VDD* VSS1
VSS1
MGW770
For test purposes only: The maximum forward current is 5 mA. The maximum reverse voltage is 5 V.
Fig.54 Device protection diagram.
2004 May 17
69
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
26 TRAY INFORMATION
PCF8811
handbook, full pagewidth
x
A C
y
1,1 1,2 1,3
2,1 2,2
3,1
x,1
D B
F
1,y
x,y
E
MGU295
Fig.55 Tray details.
Table 30 Tray dimensions DIM. A
handbook, halfpage
DESCRIPTION pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction tray width; x direction tray width; y direction number of pockets in x direction number of pockets in y direction
VALUE 13.77 mm 4.45 mm 12.55 mm 2.41 mm 50.80 mm 50.80 mm 3 10
B C D E
PCF8811-1
F x
MGW771
y
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientation and position of the type name on the die surface.
Fig.56 Tray alignment.
2004 May 17
70
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
27 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
PCF8811
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 28 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 29 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 May 17
71
Philips Semiconductors
Product specification
80 x 128 pixels matrix LCD driver
PCF8811
Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 30 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2004 May 17
72
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R15/03/pp73
Date of release: 2004
May 17
Document order number:
9397 750 13144

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